Intel Agilex team announces 400Gbps FPGAs • The Register

You may not be capable to get your palms on a Falcon Shores XPU for an additional two years, however Intel has some shiny new 400Gbps FPGAs so that you can play with whilst you wait.

Lower than every week after canning its Rialto Bridge GPUs and delaying its Falcon Shores XPU – mainly guaranteeing that AMD will beat them to market with a converged CPU-GPU for the datacenter – Intel popped into chat to remind everybody that its Agilex crew remains to be making FPGAs.

The chipmaker’s newest addition to its FPGA line-up is the Agilex 7 with F-Tile, which the corporate boasts has the quickest FPGA transceivers available on the market.

FPGAs are employed in a wide range of workloads – usually the place ASICs could not provide sufficient flexibility and general-purpose compute cannot obtain desired efficiency latency – together with telecommunications, datacenter, networking, and even crypto mining and high-frequency buying and selling. Within the case of Intel’s latest Agilex chips, the cardboard goals to deal with information and bandwidth-intensive workloads frequent in datacenters and high-speed networks.

The F-Tile a part of the identify comes from the usage of Intel’s heterogenous chiplet structure and multi-die interconnect bridge (EMIB) packaging tech, which permits the corporate to append further performance tuned to particular markets or functions to a standard FPGA block.

Particularly, the F-Tile is a financial institution of high-speed transceivers hooked up to the primary FPGA die. In line with Intel’s docs, the F-Tile sports activities 20 PAM4 transceivers in complete, together with 4 “high-speed” channels working at 116Gbps and 16 general-purpose channels operating at 58Gbps. In comparison with earlier FPGAs, Intel says the brand new chip gives about twice the bandwidth per channel, whereas consuming much less energy.

The FPGA additionally includes a devoted Ethernet chiplet good for 400Gbps. Connectivity to the host is achieved utilizing both PCIe 5.0 or CXL 1.1, each of that are able to round 64GBps of bandwidth. Nevertheless, that does imply for optimum efficiency you will must pair these with both Intel’s long-delayed Sapphire Rapids CPUs or AMD’s new Epyc 4 chips. Pop this factor in an older Ice Lake or AMD Milan system and you are going to max out at round 256Gbps and certain a lot lower than that.

The chip itself relies on Intel’s getting old 10nm manufacturing course of, which first began exhibiting up in Cannon Lake chips 5 years in the past. Nevertheless, that is probably not the case for for much longer. Earlier this week, Taiwanese newspaper UDN reported Intel China government Wang Rui saying that the corporate had finalized the design and had taped out its 18A and 20A – equal to 1.8nm and 2nm – course of nodes.

Intel maintains that the method nodes will likely be manufacture prepared by 2024, arriving in its Apollo Lake CPUs the identical 12 months. Nicely, if they are not delayed or canceled first. ®