US Department of Energy solicits AMD’s help with nuke sims • The Register

AMD will be a part of Intel in supporting Sandia Nationwide Lab’s efforts to develop novel reminiscence tech to be used in Division of Power (DoE) nuclear weapons simulations.

The contract, awarded beneath the Superior Reminiscence Know-how (AMT) program, is funded by the DoE’s Nationwide Nuclear Safety Administration (NNSA) as a part of its post-Exascale Computing Initiative.

The NNSA is the department of the DoE answerable for sustaining and lengthening the lifespan and effectiveness of the US strategic arsenal. Because the American bans on atmospheric testing in 1963 and underground testing in 1996, US army analysis and growth has relied closely on supercomputers to simulate the damaging potential of nuclear weapons.

In keeping with DoE scientists, many of those simulations profit from improved reminiscence efficiency due to the sheer variety of parameters at play in nuclear explosions. In keeping with ASC Program Director Thuc Hoang, rising reminiscence applied sciences have the potential to spice up utility efficiency by an element of 40.

“We’re pursuing reminiscence bandwidth and latency enhancements,” defined James Laros, undertaking lead at Sandia, in a statement. “If profitable, this effort will positively have an effect on each elements of reminiscence programs for our superior and commodity know-how platforms.”

AMD is not the primary chipmaker the DoE has tapped to assist it pace up its simulations. In December, the DoE awarded an identical contract to Intel, which sarcastically had canned its Optane reminiscence division months earlier.

On the time, we discovered that a lot of the analysis being carried out was into strategies of boosting the efficiency of current DDR reminiscence. “Our aim with the AMT program is to alter how DRAM is organized and assist the DRAM distributors to design and ship superior merchandise,” Intel’s Josh Fryman beforehand instructed The Register.

Nevertheless, it seems this is not the one know-how being explored. In Sandia’s newest announcement, the lab highlighted 3D packaging strategies utilized by each Intel and AMD to stack reminiscence vertically on prime of the CPU die. This has the advantage of lowering the entry latencies and enhancing bandwidth – two of the targets highlighted by Laros.

Intel’s just lately introduced Xeon Max CPU household definitely suits this description. The CPU stacks as much as 64GB of HBM2e atop the CPU for a most of 1TB/sec of reminiscence bandwidth feeding as much as double-wide PCIe card 56 cores. The reminiscence can both operate as a standalone pool, or along side DDR5 reminiscence.

AMD’s X-series Epyc processors make use of an identical strategy utilizing small, sooner SRAM stacked atop the chip’s core advanced die. This reminiscence expands the L3 cache to 96MB per die – for a complete of 768MB of L3 cache on the corporate’s top-tier Milan-X CPUs.

AMD can also be engaged on a household of datacenter APUs starting with the MI300. That chip, like Intel’s Xeon Max, will use HBM – 128GB to be precise – that shall be shared between a 24-core CPU and RDNA3 GPU. Nevertheless, it is unclear whether or not these APUs shall be used beneath the DoE program.

What we do know is that chipmakers will work with business companions to form the way forward for DRAM growth as a direct results of this program. In December, Intel stated it might contribute its findings again to JEDEC – the business consortium that oversees DRAM requirements.

So, whereas the DoE program could advance US nuclear technique within the close to time period, it has the potential to learn civilians too. ®