{"id":48736,"date":"2023-03-05T19:25:22","date_gmt":"2023-03-05T19:25:22","guid":{"rendered":"https:\/\/mailinvest.blog\/index.php\/2023\/03\/05\/amd-explains-how-the-new-3d-v-cache-improves-over-the-original\/"},"modified":"2023-03-05T19:26:17","modified_gmt":"2023-03-05T19:26:17","slug":"amd-explains-how-the-new-3d-v-cache-improves-over-the-original","status":"publish","type":"post","link":"https:\/\/mailinvest.blog\/index.php\/2023\/03\/05\/amd-explains-how-the-new-3d-v-cache-improves-over-the-original\/","title":{"rendered":"AMD explains how the new 3D V-Cache improves over the original"},"content":{"rendered":"

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In context:<\/strong> AMD launched the Ryzen 9 7950X3D on the finish of final month and welcomed an enthusiastic response to its second-gen 3D V-Cache regardless of some combined opinions about its usefulness in a 16-core CPU. Now they’ve shared a number of the technical particulars that specify its efficiency. <\/p>\n

AMD began mixing nodes in 2019 when it used the 7 nm node for the core advanced die (CCD) and the 12 nm node for the IO die of the Zen 2 microarchitecture. AMD just lately confirmed to Tom’s Hardware<\/a> that Zen 4 steps it as much as three nodes: the 5 nm node for the CCD, the 6 nm node for the IO die, and the 7 nm node for the V-Cache.<\/p>\n

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The V-Cache sits over the center of the CCD and the eight cores flank the edges.<\/p>\n

AMD defined a number of the challenges it confronted stacking one node onto one other throughout its latest ISSCC presentation. Each the 7950X3D<\/a> and the unique 5800X3D<\/a> have their V-Caches positioned over their common L3 caches to permit them to be related. The association additionally retains the V-Cache away from the warmth produced by the cores. Nevertheless, whereas the V-Cache suits neatly over the L3 cache within the 5800X3D, it overlaps with the L2 caches on the sides of the cores within the 7950X3D.<\/p>\n

A part of the issue was that AMD doubled the quantity of L2 cache in every core from 0.5 MB in Zen 3 to 1 MB in Zen 4. Nevertheless it labored across the further house constraints by punching holes by way of the L2 caches for the through-silicon vias (TSVs) that ship energy to the V-Cache. The sign TSVs nonetheless come from the controller within the heart of the CCD however AMD tweaked them too to cut back their footprint by 50%.<\/p>\n

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The Zen 4 L2 cache is bigger due to its bigger capability, but additionally as a result of it has TSVs passing by way of it.<\/p>\n

AMD shrunk the V-Cache down from 41 mm2<\/sup> to 36 mm2<\/sup> however maintained the identical 4.7 B transistors. TSMC fabricates the cache on a brand new model of the 7 nm node that it developed particularly for SRAM. In consequence, the V-Cache has 32% extra transistors per sq. millimeter than the CCD regardless of the CCD being manufactured on the a lot smaller 5 nm node.<\/p>\n

All the refinements and workarounds AMD applied add as much as a 25% improve in bandwidth to 2.5 TB\/s and an unspecified improve in effectivity. Not dangerous for 9 months between the primary and second generations of a supplemental chiplet. Hopefully it reveals its worth when the Ryzen 7 7800X3D arrives in a month’s time.<\/p>\n<\/p><\/div>\n