{"id":39447,"date":"2023-02-08T10:46:26","date_gmt":"2023-02-08T10:46:26","guid":{"rendered":"https:\/\/mailinvest.blog\/index.php\/2023\/02\/08\/could-risc-v-become-a-force-in-hpc-we-talk-to-the-experts-the-register\/"},"modified":"2023-02-08T10:47:27","modified_gmt":"2023-02-08T10:47:27","slug":"could-risc-v-become-a-force-in-hpc-we-talk-to-the-experts-the-register","status":"publish","type":"post","link":"https:\/\/mailinvest.blog\/index.php\/2023\/02\/08\/could-risc-v-become-a-force-in-hpc-we-talk-to-the-experts-the-register\/","title":{"rendered":"Could RISC-V become a force in HPC? We talk to the experts \u2022 The Register"},"content":{"rendered":"

<\/a>\n<\/p>\n

\n

Evaluation<\/span> The RISC-V structure seems set to turn out to be extra prevalent within the excessive efficiency computing (HPC) sector, and will even turn out to be the dominant structure, at the very least in accordance with some technical specialists within the discipline.<\/p>\n

In the meantime, the European Excessive Efficiency Computing Joint Enterprise (EuroHPC JU) has simply introduced a undertaking aimed on the improvement of HPC {hardware} and software program primarily based on RISC-V, with plans to deploy future exascale and post-exascale supercomputers primarily based on this know-how.<\/p>\n

RISC-V has been round for at the very least a decade as an open supply instruction set structure (ISA), whereas precise silicon implementations of the ISA have been coming to market over the previous a number of years.<\/p>\n

\n